Authors
Mughira Ghafoor, Rajwali Khan, Salah Ud Din, Akif Safeen, Quihui Li, Xingyue Yang, Zongmeng Yang, Jing Lu
Published in
RSC advances. Volume 15. Issue 45. Pages 38082-38094. Oct 08, 2025. Epub Oct 13, 2025.
Abstract
Recently, field-effect transistors (FETs) based on triple-layer InSe have been experimentally fabricated with a channel length of 10-20 nm. They show better performance than Si FETs in terms of transconductance and room-temperature ballistic ratio. Their device performance limits at shorter physical lengths remain to explore. We used the ab initio quantum transport simulation method to study monolayer (ML) and bilayer (BL) n-type β-InSe FETs with gate lengths (L g) of 2 and 3 nm. The on-state current (I on) values of the ML and BL n-type β-InSe FETs at both 2 and 3 nm L g can achieve the International Roadmap Technology for Semiconductors (ITRS) high-performance (HP) device standards. Specifically, the devices achieve I on values of 1236 and 648 μA μm-1 at L g = 2 nm for the ML and BL n-type β-InSe FETs, respectively, surpassing the standard on-state current (528 μA μm-1) defined in the 2013 ITRS edition for HP applications. The power-delay product (power consumption), delay time, and energy-delay product (energy consumption) of ML and BL n-type β-InSe also meet the ITRS requirements for HP applications. The ML and BL n-type β-InSe FETs can be potential candidates for future electronics at sub-3 nm physical nodes.
PMID:
41090180
Bibliographic data and abstract were imported from PubMed on 15 Oct 2025.
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