Hiring in life sciences? Share your open positions with our professional community. Read more Close

Advertisement

Reconfigurable 2D Floating-Gate Field-Effect Transistors with Graphene-Induced Interfacial Polarization for Unified Memory-Logic Integration.

Created on 05 Jul 2026

Authors

June-Chul Shin, Taegyun Park, Dong Hoon Shin, Hyun-Young Choi, Kyungmin Yang, Jiwoo Kim, Oh Yeong Gong, Hee Jae Hwang, Kenji Watanabe, Takashi Taniguchi, Yeonwoong Jung, Cheol Seong Hwang, Gwan-Hyoung Lee

Published in

ACS nano. Jul 05, 2026. Epub Jul 05, 2026.

Abstract

As artificial intelligence (AI) continues to proliferate, highly integrated, energy-efficient hardware with reconfigurability is essential for advancing microchip technology. Reconfigurable devices with multifunctional operations have emerged as a promising solution for such hardware, enhancing computational performance and integration efficiency. However, conventional reconfigurable devices suffer from limited functionality and the need for multiple gates, which increases system complexity and manufacturing costs, rendering them fundamentally limited for implementation in system-level applications. This work demonstrates reconfigurable floating-gate field-effect transistors (R-FGFETs) based on van der Waals (vdW) heterostructures that unify reconfigurable transistor and nonvolatile memory functionalities within a single-gate architecture. By exploiting graphene-induced interfacial polarization and engineering the dielectric stack, R-FGFET achieves four distinct electronic states─metallic, n-type semiconductor, p-type semiconductor, and insulating. Moreover, the R-FGFET exhibits excellent nonvolatile memory performance, featuring a sub-90 ns switching speed and robust data retention exceeding 10 years, allowing the configured states to be maintained without additional power. By incorporating these R-FGFETs into reconfigurable combinatorial computing units, programmable logic and arithmetic operations can be feasibly implemented with minimal overhead. This work offers a potential pathway to highly integrated, reconfigurable processors based on vdW heterostructures, providing an area-efficient solution.

PMID:
42402028
Bibliographic data and abstract were imported from PubMed on 05 Jul 2026.

Read full publication at:
Please sign in to see all details.

Advertisement

Stats

  • Community rating n/a 0 votes
  • Reviewers' rating n/a 0 votes
  • Your rating

1-terrible, 9-excellent. How would you rate this publication? Sign in in to submit your rating.

  • Recommendations n/a n/a positive of 0 vote(s)
  • Views 2
  • Comments 0

Recommended by

  • No recommendations yet.

Post a comment

You need to be signed in to post comments. You can sign in here.

Comments

There are no comments yet.

Advertisement