Real-time FPGA prototyping of joint blind equalization with ZF-NL-RSSE for data center interconnects.

Authors

Zhouhao Yang, Jiliang Liu, Yang Ou, Fangxu Lv, Mingche Lai, Jiaqing Xu, Xingyun Qi, Zhang Luo, Chaolong Xu, Xiaoyue Hu, Cewen Liu

Published in

Optics letters. Volume 51. Issue 15. Pages 4080-4083. Aug 01, 2026.

Abstract

To maximize power efficiency and system simplicity, blind equalization is widely utilized in high-speed intensity modulation/direct detection (IM/DD) systems, enabling the cost-efficient deployment in data center interconnects (DCI). Meanwhile, recognized as the theoretically optimal equalizer, maximum likelihood sequence estimation (MLSE) is recommended for broad implementation, particularly in high-speed IM/DD systems. However, conventional MLSE faces challenges due to its inability to blindly estimate both linear and nonlinear channel distortions, coupled with its high implementation complexity. This Letter proposes and experimentally demonstrates a joint blind equalization scheme featuring zero-forcing nonlinear reduced-state sequence estimation (ZF-NL-RSSE) in a real-time 80-Gbps PAM-4 transmission system based on an FPGA chip. Experimental results show that over 5-km single-mode fiber (SMF) transmission, the ZF-NL-RSSE scheme achieves rapid blind convergence, attaining a BER performance superior to traditional FFE and VDFE and comparable to the full-state ZF-NL-MLSE, while significantly lowering computational complexity.

PMID:
42537118
Bibliographic data and abstract were imported from PubMed on 01 Aug 2026.

Read full publication at:
Please sign in to see all details.

Stats

1-terrible, 9-excellent. How would you rate this publication? Sign in in to submit your rating.

Post a comment

You need to be signed in to post comments. You can sign in here.

Comments

There are no comments yet.