Wafer-Scale 3D Integration for High-Density Multi-Valued Neuromorphic Logic.

Authors

Chang-Hyeon Kim, Min Seok Kim, Joong Bum Rhim, Tae In Kim, Hyuck-In Kwon, Ick-Joon Park

Published in

Advanced science (Weinheim, Baden-Wurttemberg, Germany). Pages e77437. Aug 25, 2026. Epub Aug 25, 2026.

Abstract

As conventional transistor scaling approaches fundamental limits, multi-valued logic (MVL) has emerged as a promising strategy to enhance information density and reduce circuit complexity beyond binary complementary metal-oxide-semiconductor (CMOS) technology. Here, we present a monolithic three-dimensional (3D) vertically stacked MVL architecture based on a tellurium (Te)/indium-gallium-zinc-oxide (IGZO) heterojunction field-effect transistor (H-FET) integrated with a crystallinity-enhanced Te field-effect transistor (CE-Te FET). Engineered interfacial band alignment in the H-FET induces carrier confinement and gate-tunable electron-dominated transport, enabling intrinsic ternary switching through controlled current modulation. Complementary channel engineering of the CE-Te FET via oxidation and crystallinity recovery suppresses off-state leakage and optimizes transconductance matching, stabilizing the intermediate logic state. Using low-temperature CMOS-compatible processes, we realize wafer-scale vertically stacked ternary circuits exhibiting robust three-level operation, high uniformity, and long-term stability. System-level analysis reveals substantial gains in logic density and area efficiency enabled by H-FET-assisted 3D integration. Furthermore, the ternary voltage characteristics are directly mapped to ternary weight neural networks, enabling high-accuracy handwritten digit classification. This scalable inorganic 3D MVL platform establishes a practical pathway toward high-density logic and multi-valued neuromorphic computing architectures beyond conventional binary planar scaling.

PMID:
42640131
Bibliographic data and abstract were imported from PubMed on 25 Aug 2026.

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