Wafer-scale SOT-MRAM for analog crossbar array applications.

Authors

Samuel Liu, Vivian Rogers, Chen-Yu Hu, Ming-Yuan Song, Xinyu Bao, Jean Anne C Incorvia

Published in

Science advances. Volume 12. Issue 35. Pages eaee6952. Aug 28, 2026. Epub Aug 28, 2026.

Abstract

Analog crossbar arrays consisting of emerging memory devices can alleviate the computational strain required by vector matrix multiplications for neural network applications. The ability to produce spin orbit torque-magnetic random-access memory (SOT-MRAM) at wafer-scale positions SOT-MRAM as a strong memory candidate. In this work, we fabricate and measure 300 mm-compatible SOT-MRAM with 150% tunnel magnetoresistance (TMR) ratio, fast (2 ns) and low voltage (<1 V) operation, low energy dissipation (2 pJ), low write noise (0.1%), and low device-to-device variation of 10%. SOT-MRAM characteristics were shown to be effective for inference on calibrated models. The bi-stable anisotropy and stochastic switching of SOT-MRAM was leveraged for binary neural network training, able to reach ideal accuracy for a single device. Lastly, the devices were evaluated on probabilistic graph modeling and the interplay of TMR ratio and probability distribution is analyzed. Through these results, SOT-MRAM is shown to be a uniquely effective candidate for implementation of crossbar accelerators in memory- and energy-limited applications.

PMID:
42664328
Bibliographic data and abstract were imported from PubMed on 29 Aug 2026.

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