Authors
Jihoon Yang, Sohui Yoon, Jaehong Im, Jaemin Kim, Seonghyeok Park, Jaeeun Park, Seong-Jin Kim, Zonghoon Lee, Joonki Suh, Hongsik Jeong, Mario Lanza, Dong-Hyeok Lim, Soon-Yong Kwon
Published in
Small (Weinheim an der Bergstrasse, Germany). Pages e75285. Sep 07, 2026. Epub Sep 07, 2026.
Abstract
Two-dimensional (2D) memristors are promising for low-power and high-speed neuromorphic hardware. However, their performance under circuit-level constraints remains limited because resistive switching relies on native defects, hindering precise control of filament formation. Here, we report 2D MoTe2 memristors that integrate deterministic switching-path density engineering with CMOS-compatible one-transistor-one-memristor (1T-1 M) architectures. The devices exhibit highly linear and symmetric synaptic plasticity (αp/αd = 0.019/0.2), enabled by a balanced interplay between filament formation and confinement. Furthermore, monolithic integration with silicon transistors enables gate-tunable compliance control, which suppresses variability and stabilizes array-level operation. The resulting 1T-1 M arrays exhibit a wide dynamic range (∼22×), and minimal potentiation/depression variation (7.95%/6.22%). Device-aware simulations based on multilayer perception, convolutional neural network, and autoencoder models confirm improved learning accuracy compared to passive arrays. This work establishes a materials-to-circuit design framework that links defect-path engineering with transistor-assisted current control, providing a practical pathway toward 2D neuromorphic hardware.
PMID:
42704096
Bibliographic data and abstract were imported from PubMed on 07 Sep 2026.
Read full publication at:
Please sign in
to see all details.
Advertisement
Stats
- Recommendations n/a n/a positive of 0 vote(s)
- Views 6
- Comments 0